Cache memory

ABSTRACT

A cache memory and method for operating a cache memory are provided which comprise a tag RAM, tag RAM sense amplifier circuitry, data RAM sense amplifier circuitry and decision circuitry. Timing difficulties exist in determining whether or not a hit has occurred and in outputting the data from the data RAM upon occurrence of a hit. Upon addressing a tag entry and the corresponding data entry, the tag information is output from the tag RAM and is compared with input address information. A decision is reached as to whether or not identity exists. Only when the result of that decision has been validly determined can data be output.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the general field of cache memorycircuits.

2. Description of the Related Art

Cache memory circuits are well known in the art as memory circuitrywhich may enable optimal response to the needs of a high speedprocessor. Cache memories are usable as temporary storage ofinformation, for example of information relatively recently used by theprocessor. Information in cache RAM may be stored based upon twoprinciples, namely spatial locality and temporal locality. The principleof spatial locality is based upon the fact that when data is accessed atan address, there is an above average likelihood that the data which isnext required will have an address close to that of the data which hasjust been accessed. By contrast, temporal locality is based upon thefact that there is an above average probability that data which has justbeen accessed will be accessed again shortly.

In one approach therefore, when an item of data is accessed, adjacentdata is written to cache memory in anticipation of the need to accessit, and in another, the item which is accessed is stored. A desirableapproach is to do both.

There are many different cache configurations, ranging fromdirect-mapped cache memory to fully-associative cache memory.

Although the present invention is described in the context of aset-associative cache memory, is not envisaged that it be so limited,and the architecture described and the particular circuit details areequally applicable to other types of cache.

In a typical cache memory, there is provided a so-called “tag memory”and a so-called “data memory”. Each entry in the tag memory has anassociated entry in the data memory. The tag memory typically stores themost significant bits of an address at a position in the memorydetermined by the least significant bits of the address so thatapplication of the least significant bits of the address to an addressdecoder causes the tag memory to output the stored most significant bitsof an address. Comparison is then made between the output of the tagmemory, namely the most significant bits of the stored address and themost significant bits of the address being sought. When identity occursbetween the output of the tag memory and the address being sought, thenthere is said to be a hit in the tag memory. A line or entry in the datamemory is associated with the access from the address decoder and asecond output is made which consists of the data stored at an address.If there is a hit between the address applied to the cache and the taginformation stored, then the contents of the data memory are output fromthe cache. If there is no hit, (this situation is termed a “miss”) thenthe contents of the data memory are not output.

According to the particular technique being used, a mechanism may existfor overwriting both the tag and data RAMs if no hit occurs.

It will be clear to those skilled in the art that timing difficultiesexist in determining whether or not a hit has occurred, and inoutputting the data from the data RAM upon the occurrence of a hit. Forexample, upon addressing a tag entry and the corresponding data entry,the tag information is output from the tag RAM and must then be comparedwith input address information and a decision reached as to whether ornot identity exists. Only when the result of that decision has beenvalidly determined can a gate be controlled to enable output of the datafrom the data RAM. The critical path is thus the tag RAM access.

A person skilled in the art will also be aware that memory senseamplifiers respond to differentials on bit lines or to potentials on bitlines to provide an output which corresponds to the information storedin the memory cells via bit lines, experience a delay after access tothe memory cells of concern before those inputs have a sufficientpotential difference to accurately sense the contents of the cell. Thisis due to the inherent capacitance and inductance of the bit lines. As aresult, the sense amplifiers must be clocked at an instant which issufficiently later than the memory cell access to ensure that the senseamplifier inputs are valid, and hence that the output of the senseamplifier will be valid. There is a further timing issue in that only atsome interval after clocking of the sense amplifier-this interval beingdue to the inherent delay of the sense amplifier-the sense amplifieroutputs will correspond to the memory cell contents. The outputs of thesense amplifier in a tag RAM typically form first inputs to acomparator, the comparator having second inputs formed by the mostsignificant bits of the address concerned and further having an outputfed to the above-mentioned gate. It will be appreciated by those skilledin the art that the comparator output should only indicate a hit when atag hit is genuinely present or a miss when a tag miss is present. It isundesirable that the comparator output indicate a hit or miss merelybecause its inputs are not yet valid, because for example the senseamplifier providing those inputs has not yet settled or has not yet beenenabled by the clock.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the invention there is provided a cachememory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM,data RAM sense amplifier circuitry and decision circuitry forselectively enabling said data RAM sense amplifier circuitry, saiddecision circuitry having a first input for stored tag data and a secondinput for address data, said decision circuitry having a first validstate when said tag data matches said address data and a second validstate different to said first valid state when said tag data differsfrom said address data, said decision circuitry having a control inputfor setting said decision circuitry to an invalid state different tosaid valid states, wherein said decision circuitry has first and secondnodes, said nodes being at complementary logic levels in said validoutput states and at a common potential in said invalid state.

Preferably said tag RAM sense amplifier circuitry has an enable inputfor receiving an enable signal, said cache memory further comprisingtiming circuitry having an input connected to said enable input and afirst output connected to said control input of said decision circuitry,whereby said decision circuit attains one of said first and second validstates a first predetermined interval after application of an enablesignal to said enable input of said tag RAM sense amplifier circuitry.

Advantageously said decision circuitry further comprises first currentsource circuitry for selectively applying a current to said first nodewhen said address data differs from said stored tag data and secondcurrent source circuitry for applying a second current source to saidsecond node and sensing circuitry having first and second sensingcircuitry nodes, said sensing circuitry being responsive to a potentialon said first and second nodes for establishing said first and secondvalid states on said first and second sensing circuitry nodes.

Conveniently said sensing circuitry comprises equalization circuitryresponsive to said enable input of said tag RAM sense amplifiercircuitry for selectively applying said common potential to said firstand second sensing circuitry nodes.

Preferably, said sensing circuitry comprises a latch circuit connectedbetween said first and second sensing circuitry nodes and selectivelyconnectable to said first and second nodes via a gating circuit, saidlatch circuit and said gating circuit being activated by said controlinput.

Preferably again, said second current source circuitry is connected to asecond output of said timing circuit, whereby said second current sourceis activated a second predetermined interval after said application ofsaid enable signal. Conveniently, said first current source circuitrycomprises a first transistor.

Advantageously, said tag RAM comprises a plurality of bit line pairs,each pair having an associated tag RAM sense amplifier and an associatedfirst current source, each first current source comprising a respectivefirst transistor, said first transistors being identical and of onepolarity, said first current sources being connected between one saidfirst node and a reference node, and said second current sourcecircuitry comprising a said plurality of second transistors connectedbetween said second node and said reference node, said secondtransistors being of said one polarity.

Conveniently, one of said second transistors has half the currentcarrying capability of said first transistors, and has a control gateconnected to said second output of said timing circuitry.

Conveniently, the remaining second transistors have control gatesconnected to said reference node.

Advantageously, said timing circuitry comprises a first delay circuithaving said enable input of said tag RAM sense amplifier circuitry asits input and said second output as its output and a second delaycircuitry in series therewith, said second delay circuit comprising aplurality of third transistors connected in parallel between a timingnode and said reference node, said third transistors being of said onepolarity, and a fourth transistor of opposite polarity connected betweensaid timing node and a supply rail, said timing node providing an outputto said control input.

Advantageously again, said decision circuitry further comprises logiccircuitry connected to said data RAM sense amplifier at an enableterminal thereof, said logic circuitry being responsive to said firstand second sensing circuitry nodes and providing a first predeterminedoutput for enabling said data RAM sense amplifier circuitry only inresponse to one of said valid states at said nodes.

Conveniently, said logic circuitry has a control input whereby saidlogic circuitry responds to a predetermined logic state at said controlinput to provide said predetermined output for enabling said data RAMsense amplifier circuitry in response to the other valid state.

Preferably said data RAM sense amplifier circuitry has differentialinput terminals and precharge and equalization circuitry for prechargeand equalization of said differential input terminals, said cache memoryfurther comprising OR circuitry connected to said first and secondsensing circuitry nodes, and to said precharge and equalizationcircuitry for terminating precharge and equalization when said first andsecond sensing circuitry nodes change from said invalid state to one ofsaid valid states.

Advantageously, said data RAM sense amplifier circuitry has an outputfor data stored by said data RAM, said output being at a high impedancestate when said precharge and equalization circuitry is active.

Preferably, said tag RAM sense amplifier circuitry has first and seconddifferential outputs, wherein said decision circuitry further comprisesmultiplexer circuitry having an output, said multiplexer circuitryhaving an input for said address data whereby said multiplexer circuitrypasses the state at said first differential output when said addressdata is logic 1 and the state at said second differential output whensaid address data is logic 0.

Conveniently, said first current source circuitry responds to the outputof said multiplexer circuitry.

According to a second aspect of the invention there is provided a methodof operating a cache memory having a stored tag data, an input foraddress data, a data RAM, data RAM sense amplifier circuitry anddecision circuitry for selectively enabling said data RAM senseamplifier circuitry, said decision circuitry having a first and a secondnode, the method comprising: sensing stored tag data; comparing saidstored tag data with input address data; and setting said first andsecond nodes to a common potential, wherein said comparing stepcomprises providing a first logic level on the first node and a secondopposite logic level on the second node in response to a match betweensaid stored tag data and said input address data; and providing saidsecond logic level on the first node and said second opposite logiclevel on the first node when said stored tag data differs from saidaddress data.

Advantageously said step of sensing comprises providing an enable signalto said tag RAM sense amplifier circuitry and maintaining said commonpotential on said first and second nodes for a first predeterminedinterval after application of said enable signal.

Conveniently, said decision circuitry further has a sense node and areference node, and said comparing step comprising: applying a referencecurrent to said reference node, applying a current to said sense nodewhen said input address data differs from said stored tag data after asecond interval, applying the potentials on said reference and sensenodes to a latch circuit.

Preferably, said cache memory comprises a tag RAM and a tag RAM senseamplifier, having first and second differential outputs, wherein saidcomparing step further comprises selecting one of said differentialoutputs when said address data has a first logic value, and the other ofsaid differential outputs when said address data has a second logicvalue opposite to said first logic value, and using the selected outputto control application of said current to said sense node.

According to a third aspect of the present invention there is provided acache memory having a tag RAM, tag RAM sense amplifier circuitry, a dataRAM, data RAM sense amplifier circuitry and decision circuitry forproviding a read enable signal to a read enable terminal of said dataRAM sense amplifier circuitry, said decision circuitry having a firstinput for stored tag data, a second input for address data and a pair ofintermediate nodes, a first of said intermediate nodes being at logic 1and the second being at logic 0 when said tag data matches said addressdata, the second of said intermediate nodes being at logic 1 and thefirst being at logic 0 when said tag data differs from said addressdata, said decision circuitry having a control input for setting saidnodes to a common potential, wherein said decision circuitry furthercomprises logic circuitry being responsive to said first and secondintermediate nodes and operable to provide a read enable signal to saidread enable terminal only in response to a said match, wherein saidlogic circuitry has a control input and said logic circuitry responds toa predetermined logic state at said control input to provide said readenable signal to said read enable terminal whenever said intermediatenodes have complementary levels.

According to a fourth aspect of the present invention there is provideda method of operating a cache memory having a tag RAM, tag RAM senseamplifier circuitry, a data RAM, data RAM sense amplifier circuitryhaving a read enable input, the method comprising: sensing stored tagdata; comparing said sensed tag data with input address data;establishing a first circuit condition and maintaining said firstcircuit condition until a valid comparison is achieved and uponachieving a valid comparison: establishing a second circuit conditionwhen a match is detected between said sensed tag data and said inputaddress data establishing a third circuit condition when no match isdetected, in response to said step of establishing said secondcondition: generating a read enable signal; and supplying said readenable signal to said read enable input, the method further comprising:determining an input at a control terminal to selectively provide saidread enable signal to said read enable terminal responsive to said stepof establishing said third condition.

According to a fifth aspect of the present invention there is provided acache memory having a tag RAM, tag RAM sense amplifier circuitry, a dataRAM, data RAM sense amplifier circuitry and decision circuitry, the tagRAM sense amplifier circuitry having an enable input for receiving asense amplifier enable signal, the decision circuitry having a firstinput for stored tag data, a second input for address data and a controlinput for enabling said decision circuitry, the data RAM sense amplifiercircuitry having a disable input terminal and a read input terminal,said decision circuitry providing a data read signal to said read inputterminal of said data RAM sense amplifier circuitry when a match existsbetween said stored tag data and said address data, the memory furthercomprising: timing circuitry responsive to said sense amplifier enablesignal for maintaining a first level at said control input therebyholding an output of said decision circuitry in an inactive conditionfor a given period, and thereafter applying a second level at saidcontrol input, thereby allowing said output to become active; and logiccircuitry sensing an active output of said decision circuitry forsupplying a disabling signal to said disable input terminal, therebydisabling said data RAM sense amplifier circuitry until after saidoutput of said decision circuitry becomes active.

According to a sixth aspect of the present invention there is provided amethod of operating a cache memory having a tag RAM, tag RAM senseamplifier circuitry, a data RAM, data RAM sense amplifier circuitry anddecision circuitry, the tag RAM sense amplifier circuitry having anenable input for receiving a sense amplifier enable signal, the decisioncircuitry having a first input for stored tag data, a second input foraddress data and a control input for enabling said decision circuitry,the data RAM sense amplifier circuitry having a disable input terminaland a read input terminal, the method comprising: providing a disablingsignal to said disable input terminal, thereby disabling said data RAMsense amplifier circuitry; maintaining a first level at said controlinput thereby holding an output of said decision circuitry in aninactive condition for a given period after said sense amplifier enablesignal; thereafter applying a second level at said control input,thereby allowing said output to become active; sensing the output ofsaid decision circuitry; in response to an active output, terminatingsupply of said disabling signal to said disable input terminal; andproviding a data read signal to said read input terminal of said dataRAM sense amplifier circuitry when a match exists between said storedtag data and said address data.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

An embodiment of the invention will now be described with reference tothe accompanying drawings in which:

FIG. 1 shows a block schematic diagram of a cache memory device of theprior art;

FIG. 2 shows an exemplary schematic diagram of a memory cell;

FIG. 3 shows a layout diagram for a cache memory in accordance with thepresent invention; and

FIG. 4 shows a circuit diagram of a part of a cache memory device inaccordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring first to FIG. 1, a cache memory device has an address decoder1 having an input 20 and four outputs 21-24 addressing the four rows ofa tag RAM 2, having respective addresses “00”, “01”, “10” and “11” theoutputs of the decoder simultaneously addressing the four rows of a dataRAM 3. The tag RAM 2 has four column lines 40 which are input to a firstsense amplifier block 7, the sense amplifier block 7 having four outputs41 providing first inputs to a comparator 4. A second input to thecomparator 4 is provided by a four way bus 25. The data RAM 3 has 32column lines 42 fed to a second sense amplifier block 8 which has 32output lines 33, the 32 output lines being fed to a gating circuit 5controlled by the output 26 of the comparator 4. The first senseamplifier block 7 has a clock input 27 and the second amplifier block 8has a clock input 28.

Reference numeral 10 indicates a six bit address which consists of twoleast significant bits 11 which provide the input 20 to the addressdecoder 1 and four most significant bits 12 which provide the secondinput 25 to the comparator 4.

In this simplified example, the least significant bits 11 are “01” andthe most significant bits 12 are “1010”.

In use the least significant bits 11 are supplied over input line 20 tothe address decoder 1 and the address decoder provides an output on line22, the second line of the cache which has an address “01”. Furtherinspection of FIG. 1 shows the contents of the second line of the tagRAM is “1010” which in this example corresponds to the most significantbits 12 of the address 10.

As known to those skilled in the art, the memory cells of the secondline of the tag RAM are connected by the output of the address decoderto the bit lines 40 and after a delay caused by propagation along thebit lines the inputs to the first sense amplifier block 7 are in thestate “1010”. At a predetermined time the clock input 27 to the firstsense amplifier block 7 changes state and shortly thereafter the senseamplifiers of the first sense amplifier block 7 assume the output state“1010”. This state change will typically be latched at the output ofeach of the sense amplifiers.

The input “1010” is applied to the first input of the comparator 4 andthe most significant bits 12 (also “1010”) are applied to the secondinput of the comparator 4. After a period corresponding to thepropagation delay of the comparator 4, the output line 26 will go to alogic 1 state.

Activation of the word line 22 to the second row of the tag RAM alsoactivates the second row of the data RAM 3. In a similar fashion to thetag RAM, this causes the bit lines 42 to acquire a state correspondingto the data stored in the second row of the data RAM 3, this state beingapplied to the second sense amplifier block 8 and, upon a clocktransition being applied to the corresponding clock terminal 28, theoutput lines 43 to the gating circuit 5 correspond to the contents ofthe second row of the data RAM.

At the time the comparator output line 26 goes to logic 1 the gatingcircuit 5 passes the logic state at its input to the output bus 6.

From the above discussion it will be seen that if the two senseamplifier blocks were clocked at the same time to provide a valid outputat the same time there will be an additional delay after the clockbefore the gate 5 can provide an output caused by the propagation delayof the comparator 4 in the “hit/miss” path.

Referring now to FIG. 2, an exemplary memory cell 70 will now bedescribed. It will be understood by those skilled in the art that manyother configurations of memory cell may be used. The memory cell 70comprises two cross-coupled CMOS inverters connected between a positivesupply V_(dd) and a negative supply V_(ss). The first CMOS inverterconsists of a p MOSFET 71 having its main current path connected inseries with an n MOSFET 72, the common connection between the twotransistors forming a first node 73. The second CMOS inverter likewiseconsists of a p MOSFET 74 having its main current path connected inseries with an n MOSFET 75, the common connection between the twotransistors forming a second node 74A. The first node 73 is connected tothe gates of the two transistors of the second inverter and the secondnode 74A is connected to the gates of the two transistors of the firstinverter. The first node 73 is connected via a first N-type pathtransistor 76 to a first bit line 77 and the second node 74A isconnected via a second N-type path transistor 78 to a second bit line79. The gates of the N-type path transistors 76 and 78 are connected toa word line 60.

Referring now to FIG. 3 a block schematic diagram of a cache memory isshown. The memory 50 comprises 6 areas as follows:

The first area 51 is provided for the word line decoders and drivers.

The second and third areas 52, 53 which are alongside the first area 51are a pair of memory arrays having word lines 60 extending through bothof the arrays as row lines. Arranged on the row lines are multiplememory cells of the type shown in FIG. 2. The first array 52 forms adata RAM of the cache and has relatively thin cells. By thin cells it ismeant that the transistors 71, 72, 74, 75 have a relatively low currentdrive capability. The second array 53 which lies beyond the first array52 forms the tag RAM and has relatively fat memory cells. By fat cellsit is meant that the transistors 71, 72, 74, 75 have a relatively highcurrent drive capability. The fat cells provide a substantially higherdrive capability to the bit lines of the tag RAM than is provided by thethin cells of the data RAM. The extra drive capability means that thebit lines in the tag RAM reach a valid potential level much more quicklythan those of the data RAM.

The fourth area 54, which is associated with the bit lines 77, 79 of thetag RAM, is an area for sense amplifiers for the tag RAM, which senseamplifiers are formed of thin fast transistors. The fourth area 54 alsoprovides the location for the comparator.

The fifth area 55 is the location for the sense amplifiers for the bitlines 77, 79 of the data RAM. The fifth area 55 also provides thelocation for the gating circuit and output driver circuitry of the cachememory.

The sixth and final area 56 is provided for control logic of the cachememory.

It will be seen that the floor plan of the cache memory 50 is verysimple, and allows for a common word line.

The particular floor plan shown in FIG. 3 is exemplary; it would bepossible for example to dispose the word line decoder and driver area 51between the RAM areas 52 and 53.

FIG. 4 shows part of an embodiment of a cache memory in accordance withthe invention. It will be clear to those skilled in the art that thefull circuit has plural tag bit line pairs, one common comparator andplural data bit line pairs. For simplicity only one tag bit line pairand one data bit line pair is shown. The circuitry comprises tag senseamplifier circuitry, multiplexer circuitry, comparator and timingcircuitry and data sense amplifier circuitry.

Each tag RAM complementary bit line pair 100, 101 is connected to arespective latching sense amplifier 221. The sense amplifier 221comprises cross-coupled inverters 104, 105 having a common controlterminal 106 connected to a first enable transistor 107, the connectionof the bit lines to the sense amplifier being via a first pair of Pchannel hook transistors 102, 103. The gates of the hook transistors102, 103 and the gate of the first enable transistor 107 are connectedin common to a sense amp enable input 200 described more fully laterherein. The differential output of the sense amplifier passes viarespective buffer inverters 108, 109 to the multiplexer 111 controlledby a compare address bit signal 201. The multiplexer 111 comprises twopass gates 114, 115, each comprising a P transistor and an N transistorwith a compare input 201 being connected to the gate of the N transistorof first pass gate 114 and to the gate of the P transistor of secondpass gate 115 and further comprises an inverter 116 having an inputconnected to the compare input 201 and an output connected to the Pchannel transistor of the first pass gate 114 and to the gate of the Nchannel transistor of the second pass gate 115. The outputs of the twopass gates are connected together to the gate of a first pull-down Nchannel transistor 117, whose source is connected to the groundreference potential and whose drain is connected to a first comparatorline 118. It will be understood by those skilled in the art that therewill be one first pull-down N channel transistor 117 for each bit linepair, the number of bit line pairs corresponding to the number of bitsin the tag. For the present example, assume 5 bits for the tag: hencethere will be 5 bit line pairs and 5 transistors 117, each connected tothe line 118.

The sense amp enable terminal 200 is furthermore connected via a delaycircuit 110 to the control gate of a second N type comparator transistor120, the control gates of three identical N type timing transistors 124and the control gate of a P type timing transistor 125. The secondcomparator transistor 120 is half the width or twice the length of thefirst pull-down N-channel comparator transistor 117 and has a drainconnected to a second comparator line 202 and a source connected toeach. The second comparator line 202 is also loaded with respect toearth via four parallel N type transistors 121. Each of the transistors121 has a gate which is connected to earth and each transistor 121 isidentical to the previously discussed first pull-down transistor 117.The P timing transistor 125 has a source connected to a positive supplyrail and a drain connected to a timing line 203. The timing line 203 isconnected to the commoned drains of the three identical N transistors124. The sources of the N transistors 124 are connected to earth. Thetiming line 203 is also loaded to earth by two identical N transistors126 whose gates are connected to earth. The three N transistors 124 andthe two N transistors 126 are identical in size to N-channel comparatortransistor 112. The reason for the selection of the total number oftransistors 120 and 121, and the total of transistors 124 and 126 asequal to the number of pull-down transistor 117 will now be explained.It will be recalled that there are five bit line pairs and hence fiveidentical transistors 117. If all five of the transistors 117 are off(this corresponds to a hit), it is advantageous for the secondcomparator line 202 to have the same impedance to earth as the line 118,and to achieve this, five transistors are required. Likewise for line203, to achieve the correct timing conditions.

The first and second comparator lines 118 and 202 are connected viaecond P type hook transistors 119, 112 to a comparator sense amplifier131 comprising ross-coupled inverters, the sense amplifier side of thesecond hook transistors 119 and 122 being connected to a precharge andequilibration circuit 123. Continuing to refer to FIG. 3 it will be seenthat the precharge and equilibration circuit 123 comprises three P typetransistors, having commoned control gates connected to the senseamplifier enable terminal 200. Two of the transistors connect arespective comparator line to the positive supply terminal and the thirdtransistor connects the two comparator lines together when the senseamplifier enable terminal is at a low potential.

The second hook transistors 119, 122 have commoned control gatesconnected to the drain of an N type enable transistor 128. The controlgate of N type enable transistor 128 is fed from the output of aninverter 127 and its source is connected to earth. The input to theinverter 127 is provided by the previously discussed timing line 203.The commoned gates of the second hook transistors 119, 122 also formsthe enable terminal of the comparator sense amplifier 131.

The differential output of the comparator sense amplifier 131 appears ona first comparator output node 129 corresponding to first comparatorline 118, and on a second comparator output node 130 corresponding tosecond comparator line 202. The output is fed to the inputs ofrespective inverters 132, 133. The inverter 132 which is connected tothe first comparator output node 129 has an output 135 and the secondinverter 133 whose input is connected to the second comparator outputnode 132 has an output 138. The output 135 of the first inverter 132 isconnected to one input of a two-input AND gate 126, the other input ofwhich is provided at an input terminal 134. The output terminal 137 ofthe AND gate 136 forms one input of a two-input NOR gate 139, the otherinput of which is the output terminal 138 of the second inverter 133.The output terminal of the NOR gate 139 is connected to the input of afurther inverter 141.

A differential pair of data RAM bit lines 160, 161 is connected viathird P channel hook transistors 162, 163 to a cross-coupled invertertype data RAM sense amplifier 164. The commoned gates of the third hooktransistors 162, 163 are connected to the output of the further inverter141. The output of the inverter 141 forms the control gate terminal ofan N channel data sense amp enable transistor 142 having a sourceconnected to the ground reference terminal and a drain connected to theenable terminal of the data RAM sense amplifier 164. It will beunderstood that there are plural data RAM bit line pairs, in numberequal to the number of data bits. Thus, for example, there may be 32data RAM bit line pairs, accessed by 32 parallel enable transistors 142.The differential output of the data RAM sense amplifier 164 is connectedvia a first and a second output inverter 165, 166 to a data senseamplifier output circuit. The data sense amplifier output circuitconsists of a P channel pull-up transistor 168 having a control gateconnected via a further output inverter 167 to the output of the firstoutput inverter 165 and an N channel output transistor 169 connected tothe output of the second output inverter 166. The drains of the Pchannel output transistor 168 and the N channel output transistor 169are connected together at a common output terminal 170. The source ofthe P channel output transistor 168 is connected to the positive supplyterminal and the source of the N channel output transistor 169 isconnected to the ground reference terminal.

A read enable signal causes a precharge potential to be disconnectedfrom the bit lines, and a memory cell to become connected to thedifferential bit lines 100, 101. This causes the bit line potentials toseparate, and the separation to propagate along the bit lines.

The sense amplifier enable terminal 200 may receive the output of adummy bit line or other suitable timing circuitry triggered by the readenable signal, to ensure that the first pair of hook transistors 102,103 remain conductive until a suitable time has elapsed for propagationalong the tag RAM bit lines to occur. Once that time has elapsed, thevoltage on the sense amplifier enable input 200 makes a transition fromlow to high. This transition causes the first pair of hook transistors102, 103 to become substantially open circuit (“off-hook”). Shortlyafterwards the sense amplifier 221 latches by virtue of activation asthe sense amplifier enable transistor 107 conducts. At substantially thesame time, the precharge and equilibration circuit 123 of the comparatorturns off.

Assume for example that the first bit line 100 is connected to atransistor storing logic 1 and the second bit line 101 is connected to atransistor storing logic 0. Then the sense amplifier 104, 105 latcheswith the input of first inverter 108 at logic 1 and the input of thesecond inverter at logic 0. Thus the output 112 of the first inverter108 will be at logic 0 and the output 113 of the second inverter 109will be at logic 1. If the compare address bit input 201 is at logic 1the first pass gate 114 will connect to the multiplexer output 205 thelogic 0 at the output of the first inverter 108. If instead the compareaddress bit input 201 is at logic 0, then the multiplexer 111 willprovide at its output the logic 1 appearing at the output of the secondinverter 109.

Thus for a hit defined as equality between the state stored on the bitline pair and the state of the compare address input, the multiplexeroutput 205 will have a logic 0. If all of the tag RAM bit line pairshave a hit with their compare inputs, all outputs 205 will be at logic0, and all transistors 117 will be non-conducting.

The delay circuitry 110 is dimensioned to delay the sense amp enabletransition to cause the comparator transistor 120 to turn on atsubstantially the same time as any logic 1 appears at the gate of thefirst pull-down transistor 117.

This later transition which causes the half-size comparator transistor120 to switch on, pulls the second comparator line 202 to earth. At thesame time the P timing transistor 125 which was pulling the third line203 up to the positive supply terminal is turned off and the three Ntiming transistors 124 are turned on to rapidly pull the third line 203to earth. This in turn causes the enable transistor 128 to switch on, byvirtue of the inverter 127 and the turning on of the enable transistor128 causes the second hook transistors 119, 122 to turn on and, at thesame time the sense amplifier 131 to become enabled.

Prior to this time, the sense amplifier lines 129, 130 are both at highpotential due to the precharge and equilibration circuit. This has theeffect that the outputs 135 and 138 of the inverters 132, 133 are bothat logic 0 which means that the output of the NOR 139 will be at logic0.

Where there has been no match between the compare address at input 201and the output of the sense amplifier 104, 105, it will be recalled thatthe multiplexer 111 provides at its output a logic 1. This causes thefirst pull-down transistor 117 to turn on pulling the first comparatorline 118 from the precharge level of the positive supply down towardsearth. Note that the first pull-down transistor 117 conducts current attwice the rate of the half-size comparator transistor 120. Hence for amiss, the first comparator line 118 will always be more negative thanthe second comparator line 202. However, for a hit, all of thetransistors 117 will be off, and the half-size transistor 120 is on.This ensures that the second comparator line 202 is always more negativethan the first comparator line 118.

Hence for a miss, the sense amplifier 131 latches with the terminal 129at logic 0 and the terminal 130 at logic 1 and vice-versa for a hit. Thelogic level on the second terminal 129 is inverted by inverter 132 online 135 and compared in gate 136 with the input at the input terminal134.

Where a hit occurs, line 130 is at logic 0 and line 129 at logic 1. Thelogic 0 at line 130 is inverted in inverter 133 to provide a logic 1 atline 138. It should be noted that prior to sensing by the comparatorboth lines 129 and 130 are at logic 1: as a result both lines 135 and138 are at logic 0. Once sensing occurs lines 135 and 138 becomecomplementary. For a hit, line 138 makes a transition to 1. Beforesensing the NOR gate 139 has inputs of 0,0 (giving an output of 1) andafter sensing, inputs of 0,1 (giving an output of 0). The output of theNOR gate 139 is inverted by the inverter 141 to control the data RAMsensing circuitry.

For a miss, the situation varies according to the input at terminal 134.If no action is desired, then 134 is set to 0. Prior to sensing, bothinputs to AND gate 06 are at 0, giving a 0 output. The NOR 139 has 0 atboth inputs giving a 1 output. After sensing, the AND 136 remains at 0and the NOR output remains at 1.

If data read is needed even on miss, the terminal 134 is set to 1. Thenwhen the line 135 goes to 1 after sensing, the NOR gate makes atransition to logic 0.

Whenever the NOR gate output goes to 0, the output of the inverter 141goes to logic 1. The effect of this is as follows: Prior to theappearance of any logic 1 at the output of the further inverter 141,transistor 142 is turned off and the third hook transistors 162, 163 aredisabled. Precharge circuitry 230, similar to circuitry 220 and 123,causes both of the terminals of the data RAM sense amplifier 164 to beat logic 1. This in turn causes the application of a negative potentialto the N type output transistor 169 causing it to turn off and apositive potential to be applied to the gate of the P type outputtransistor 168 causing it to turn off. As a consequence, unless anduntil the data RAM sense amp 164 is enabled, so as to providecomplementary outputs, the output terminal will be at a high impedancetristate condition.

When however a logic 1 is provided at the output of the inverter 141,this renders non-conductive the third hook transistors 162, 163 andturns on the transistor 142 thereby enabling the third sense amplifier164.

As a result it will be seen that where terminal 134 is at logic 0, theoutput of the comparator circuitry is always at logic 0 except when ahit has occurred.

It will be clear to those skilled in the art that timing difficultiesexist in determining whether or not a hit has occurred, and inoutputting the data from the data RAM upon the occurrence of a hit. Forexample, upon addressing a tag entry and the corresponding data entry,the tag information is output from the tag RAM and must then be comparedwith input address information and a decision reached as to whether ornot a hit or miss has occurred. Only when the result of that decisionhas been validly determined can data from the data RAM be output.

All of the above U.S. patents, U.S. patent application publications,U.S. patent applications, foreign patents, foreign patent applicationsand non-patent publications referred to in this specification and/orlisted in the Application Data Sheet, including but not limited to[insert list], are incorporated herein by reference, in their entirety.

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

What is claimed is:
 1. A cache memory having a tag RAM, tag RAM senseamplifier circuitry, a data RAM, data RAM sense amplifier circuitry anddecision circuitry for selectively enabling said data RAM senseamplifier circuitry, said decision circuitry having a first input forstored tag data and a second input for address data, said decisioncircuitry having a first valid state when said tag data matches saidaddress data and a second valid state different to said first validstate when said tag data differs from said address data, said decisioncircuitry having a control input for setting said decision circuitry toan invalid state different to said valid states, wherein said decisioncircuitry has first and second nodes, said nodes being at complementarylogic levels in said valid output states and at a common potential insaid invalid state.
 2. A cache memory according to claim 1, wherein saidtag RAM sense amplifier circuitry has an enable input for receiving anenable signal, said cache memory further comprising timing circuitryhaving an input connected to said enable input and a first outputconnected to said control input of said decision circuitry, whereby saiddecision circuit attains one of said first and second valid states afirst predetermined interval after application of an enable signal tosaid enable input of said tag RAM sense amplifier circuitry.
 3. A cachememory as claimed in claim 2, wherein said decision circuitry furthercomprises first current source circuitry for selectively applying acurrent to said first node when said address data differs from saidstored tag data and second current source circuitry for applying asecond current source to said second node and sensing circuitry havingfirst and second sensing circuitry nodes, said sensing circuitry beingresponsive to a potential on said first and second nodes forestablishing said first axed second sensing circuitry nodes.
 4. A cachememory as claimed in claim 3, wherein said sensing circuitry compriseequalization circuitry responsive to said enable input of said tag RAMsense amplifier circuitry for selectively applying said common potentialto said first and second sensing circuitry nodes.
 5. A cache memory asclaimed in claim 3, wherein said sensing circuitry comprises a latchcircuitry connected between said first and second sensing circuitrynodes and selectively connectable to said first and second nodes via agating circuitry, said latch circuit and said gating circuit beingactivated by said control input.
 6. A cache memory as claimed in claim5, wherein said second current source circuitry is connected to a secondoutput of said timing circuitry, whereby said second current source isactivated a second predetermined interval after said application of saidenable signal.
 7. A cache memory as claimed in claim 6, wherein saidfirst current source circuitry comprises a first transistor.
 8. A cachememory as claimed in claim 6, wherein said tag RAM comprises a pluralityof bit line pairs, each pair having an associated tag RAM senseamplifier and an associated first current source, each first currentsource comprising a respective first transistor, said first transistorsbeing identical and of one polarity, said first current sources beingconnected between one said first node and a reference node, and saidsecond current source circuitry comprising a corresponding plurality ofsecond transistors connected between said second node and said referencenode, said second transistors being of said one polarity.
 9. A cachememory as claimed in claim 8, wherein one of said second transistors hashalf the current-carrying capability of said first transistors, and hasa control gate connected to said second output of said timing circuitry.10. A cache memory as claimed in claim 9, wherein the remaining secondtransistors have control gates connected to said reference node.
 11. Acache memory as claimed in claim 8, wherein said timing circuitrycomprises a first delay circuit having said enable input of said tag RAMsense amplifier circuitry as its input and said second output as itsoutput and a second delay circuit in series therewith, said second delaycircuit comprising a plurality of third transistors connected inparallel between a timing node and said reference node, said thirdtransistors being of said one polarity, and a fourth transistor ofopposite polarity connected between said timing node and a supply rail,said timing node providing an output to said control input.
 12. A cachememory as claimed in claim 11, wherein said decision circuitry furthercomprises logic circuitry connected to said data RAM sense amplifier atan enable terminal thereof, said logic circuitry being responsive tosaid first and second sensing circuitry nodes and providing a firstpredetermined output for enabling said data RAM sense amplifiercircuitry only in response to one of said valid states at said nodes.13. A cache memory as claimed in claim 12, wherein said logic circuitryhas a control input whereby said logic circuitry responds to apredetermined logic state at said control input to provide saidpredetermined output for enabling said data RAM sense amplifiercircuitry in response to the other valid state.
 14. A cache memory asclaimed in claim 11, wherein said data RAM sense amplifier circuitry hasdifferential input terminals and precharge and equalization circuitryfor precharge and equalization of said differential input terminals,said cache memory further comprising OR circuitry connected to saidfirst and second sensing circuitry nodes, and to said precharge andequalization circuitry for terminating precharge and equalization whensaid first and second sensing circuitry nodes change from said invalidstate to one of said valid states.
 15. A cache memory as claimed inclaim 14, wherein said data RAM sense amplifier circuitry has an outputfor data stored by said data RAM, said output being at a high impedancestate when said precharge and equalization circuitry is active.
 16. Acache memory as claimed in claim 1, wherein said tag RAM sense amplifiercircuitry has first and second differential outputs, wherein saiddecision circuitry further comprises multiplexer circuitry having anoutput, said multiplexer circuitry having an input for said address datawhereby said multiplexer circuitry passes the state at said firstdifferential output when said address data is logic 1 and the state atsaid second differential output when said address data is logic
 0. 17. Acache memory as claimed in claim 16, wherein said first current sourcecircuitry responds to the output of said multiplexer circuitry.
 18. Amethod of operating a cache memory having a stored tag data, an inputfor address data, a data RAM, data RAM sense amplifier circuitry anddecision circuitry for selectively enabling said data RAM senseamplifier circuitry, said decision circuitry having a first and a secondnode, the method comprising: sensing stored tag data; comparing saidstored tag data with input address data; and setting said first andsecond nodes to a common potential, wherein said comparing stepcomprises: providing a first logic level on the first node and a secondopposite logic level on the second node in response to a match betweensaid stored tag data and said input address data; and providing saidsecond logic level on the first node and said second opposite logiclevel on the first node when said stored tag data differs from saidaddress data.
 19. A method of operating a cache memory according toclaim 18, wherein said step of sensing comprises providing an enablesignal to said tag RAM sense amplifier circuitry and maintaining saidcommon potential on said first and second nodes for a firstpredetermined interval after application of said enable signal.
 20. Amethod of operating a cache memory as claimed in claim 19, wherein saiddecision circuitry further has a sense node and a reference node, andsaid comparing step comprises: applying a reference current to saidreference node, applying a current to said sense node when said inputaddress data differs from said stared tag data after a second interval,applying the potentials on said reference and sense nodes to a latchcircuit.
 21. A method of operating a cache memory as claimed in claim20, wherein said cache memory comprises a tag RAM and a tag RAM senseamplifier, having first and second differential outputs, wherein saidcomparing step further comprises selecting one of said differentialoutputs when said address data has a first logic value, and the other ofsaid differential outputs when said address data has a second logicvalue opposite to said first logic value, and using the selected outputto control application of said current to said sense node.
 22. A cachememory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM,data RAM sense amplifier circuitry and decision circuitry for providinga read enable signal to a read enable terminal of said data RAM senseamplifier circuitry, said decision circuitry having a first input forstored tag data, a second input for address data and a pair ofintermediate nodes, a first of said intermediate nodes being at logic 1and the second being at logic 0 when said tag data matches said addressdata, the second of said intermediate nodes being at logic 1 and thefirst being at logic 0 when said tag data differs from said addressdata, said decision circuitry having a control input for setting saidnodes to a common potential, wherein said decision circuitry furthercomprises logic circuitry being responsive to said first and secondintermediate nodes and operable to provide a read enable signal to saidread enable terminal only in response to said match, wherein said logiccircuitry has a control input and said logic circuitry responds to apredetermined logic state at said control input to provide said readenable signal to said read enable terminal whenever said intermediatenodes have complementary levels.
 23. A cache memory according to claim22, wherein said tag RAM sense amplifier circuitry has an enable inputfor receiving a sense amplifier enable signal, said cache memory furthercomprising timing circuitry having an input connected to said enableinput and a first output connected to said control input of saiddecision circuitry, whereby said nodes of said decision circuit aremaintained at said common potential for a first predetermined intervalafter application of an enable signal to said sense amplifier enableinput.
 24. A cache memory as claimed in claim 23, wherein said decisioncircuitry further comprises a sense node and a reference node, firstcurrent source circuitry for applying a current to said sense node whensaid address data differs from said stored tag data, second currentsource circuitry for applying a reference current source to saidreference node and sensing circuitry having said first and secondintermediate nodes, said sensing circuitry being responsive to apotential on said sense and reference nodes for establishing said logicstates thereon.
 25. A method of operating a cache memory having a tagRAM, tag RAM sense amplifier circuitry, a data RAM, data RAM senseamplifier circuitry laving a read enable input, the method comprising:sensing stored tag data; comparing said sensed tag data with inputaddress data; establishing a first circuit condition and maintainingsaid first circuit condition until a valid comparison is achieved andupon achieving a valid comparison: establishing a second circuitcondition when a match is detected between said sensed tag data and saidinput address data; establishing a third circuit condition when no matchis detected, in response to said step of establishing said secondcondition: generating a read enable signal; and supplying said readenable signal to said read enable input, the method further comprising:determining an input at a control terminal to selectively provide saidread enable signal to said read enable terminal responsive to said stepof establishing said third condition.
 26. The method of claim 25,wherein said cache memory comprises a comparator circuit having twocircuit nodes, wherein in said circuit first condition said two nodesare at a common potential, in said second and third circuit conditionssaid nodes have complementary logic states, with one of said nodes beingat logic value 1 in said second circuit condition and the other of saidnodes being at logic 1 in said third circuit condition.
 27. The methodof claim 26, wherein said step of sensing stored tag data comprisessupplying a sense signal to said tag RAM sense amplifier circuitry toinitiate sensing, said step of establishing said first circuit conditioncomprises applying said common potential to said two circuit nodes, andsaid step of maintaining said first circuit condition until a validcomparison is achieved comprises providing a timing signal apredetermined time after said supplying of said sense signal to activatesaid comparator circuit.
 28. The method of claim 27, wherein saidcomparator circuit comprises a latch circuit, and said step ofactivating said comparator circuit comprises enabling said latchcircuit.
 29. The method of claim 28, wherein said comparing stepcomprises applying a reference current to a first comparator terminal,in response to no said match applying a current to a second comparatorterminal, and connecting said latch circuit to said first and secondcomparator terminals.
 30. A cache memory having a tag RAM, tag RAM senseamplifier circuitry, a data RAM, data RAM sense amplifier circuitry anddecision circuitry, the tag RAM sense amplifier circuitry having anenable input for receiving a sense amplifier enable signal, the decisioncircuitry having a first input for stored tag data, a second input foraddress data and a control input for enabling said decision circuitry,the data RAM sense amplifier circuitry having a disable input terminaland a read input terminal, said decision circuitry providing a data readsignal to said read input terminal of said data RAM sense amplifiercircuitry when a match exists between said stored tag data and saidaddress data, the memory further comprising: timing circuitry responsiveto said sense amplifier enable signal for maintaining a first level atsaid control input thereby holding an output of said decision circuitryin an inactive condition for a given period, and thereafter applying asecond level at said control input, thereby allowing said output tobecome active; and logic circuitry sensing an active output of saiddecision circuitry for supplying a disabling signal to said disableinput terminal, thereby disabling said data RAM sense amplifiercircuitry until after said output of said decision circuitry becomesactive.
 31. A cache memory as claimed in claim 30, wherein said data RAMsense amplifier circuitry has an output for data stored by said dataRAM, said output being at a high impedance state when said data RAMsense amplifier circuitry is disabled.
 32. A cache memory as claimed inclaim 31, wherein said data RAM sense amplifier circuitry hasdifferential input terminals and precharge and equalization circuitryfor precharge and equalization of said differential input terminals,said disable input terminal being operative upon termination of saiddisabling signal to terminate said precharge and equalization.
 33. Acache memory as claimed in claim 30, wherein said decision circuitry hastwo circuit nodes, said decision circuitry having a first condition inwhich said two circuit nodes have a common potential, said firstcondition corresponding to an inactive output and a second condition inwhich said two nodes are at complementary logic levels, corresponding tosaid active output.
 34. A cache memory as claimed in claim 33, whereinin said second condition a match is indicated when a predetermined oneof said nodes is at logic 1 and a miss is indicated when said one ofsaid nodes is at logic
 0. 35. A cache memory as claimed in claim 34,wherein said decision circuitry further comprises second logic circuitryconnected to said data read terminal, said logic circuitry beingresponsive to said circuit nodes and providing a data read signal tosaid read input terminal of said data RAM sense amplifier circuitry whensaid one of said nodes is at logic
 1. 36. A cache memory as claimed inclaim 35, wherein said second logic circuitry is responsive to apredetermined logic level at a control input thereof to provide saiddata read signal when said two nodes have complementary logic levelsregardless of whether said one of said nodes or the other of said nodesis at logic
 1. 37. A cache memory as claimed in claim 30, wherein saiddecision circuitry has a first node and a reference node, first currentsource circuitry for selectively applying a current to said first nodewhen said address data differs from said stored tag data and referencecurrent source circuitry for applying a reference current source to saidreference node and latching circuitry having first and second latchingcircuitry nodes, said latching circuitry being responsive to a potentialon said first and reference nodes for establishing said complementarylogic levels on said first and second latching circuitry nodes.
 38. Acache memory as claimed in claim 37, further comprising equalizationcircuitry responsive to said enable input of said tag RAM senseamplifier circuitry for selectively applying said common potential tosaid first and second latching circuitry nodes.
 39. A cache memory asclaimed in claim 37, wherein said latching circuitry is selectivelyconnectable to said first and reference nodes via a gating circuit, saidlatching circuitry and said gating circuit being activated by an outputof said timing circuitry.
 40. A cache memory as claimed in claim 39,wherein said reference current source circuitry is connected to a secondoutput of said timing circuit, whereby if said reference current sourceis activated a predetermined interval after said application of saidsense amplifier enable signal.
 41. A cache memory as claimed in claim40, wherein said tag RAM comprises a plurality of bit line pairs, eachpair having an associated tag RAM sense amplifier and an associatedfirst current source, each first current source comprising a respectivefirst transistor, said First transistors being identical and of onepolarity, said first current sources being connected between one saidfirst node and a reference node, and said reference current sourcecircuitry comprising a said plurality of reference transistors connectedbetween said second node and said reference node, said referencetransistors being of said one polarity.
 42. A cache memory as claimed inclaim 41, wherein each of said first transistors has a predeterminedcurrent-carrying capability, one of said reference transistors has halfsaid predetermined current-carrying capability of said firsttransistors, and has a control gate connected to said second output ofsaid timing circuitry.
 43. A cache memory as claimed in claim 42,wherein the remaining second transistors have control gates connected tosaid reference node.
 44. A method of operating a cache memory having atag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM senseamplifier circuitry and decision circuitry, the tag RAM sense amplifiercircuitry having an enable input for receiving a sense amplifier enablesignal, the decision circuitry having a first input for stored tag data,a second input for address data and a control input for enabling saiddecision circuitry, the data RAM sense amplifier circuitry having adisable input terminal and a read input terminal, the method comprising:providing a disabling signal to said disable input terminal, therebydisabling said data RAM sense amplifier circuitry; maintaining a firstlevel at said control input thereby holding an output of said decisioncircuitry in an inactive condition for a given period after said senseamplifier enable signal; thereafter applying a second level at saidcontrol input, thereby allowing said output to become active; sensingthe output of said decision circuitry; in response to an active output,terminating supply of said disabling signal to said disable inputterminal; and providing a data read signal to said read input terminalof said data RAM sense amplifier circuitry when a match exists betweensaid stored tag data and said address data.
 45. A method of operating acache memory as claimed in claim 44, further comprising maintaining anoutput of said data RAM sense amplifier circuitry in a high impedancestate while said data RAM sense amplifier circuitry is disabled.
 46. Amethod as claimed in claim 45, wherein the decision circuitry furthercomprises precharge and equalization circuitry, the method comprising,in response to said sense amplifier enable signal, precharging andequalization of differential input terminals of said decision circuitry;and before said step of terminating said disabling signal, ceasingprecharge and equalization of said differential input terminals.
 47. Amethod as claimed in claim 44, wherein said decision circuitry has twocircuit nodes, said decision circuitry having a first condition in whichsaid two circuit nodes have a common potential, said first conditioncorresponding to an inactive output and a second condition in which saidtwo nodes are at complementary logic levels, corresponding to saidactive output.
 48. A method as claimed in claim 44, wherein saiddecision circuitry has a first node and a reference node, the methodcomprising: applying a current to said first node when said address datadiffers from said stored tag data; applying a reference current sourceto said reference node; wherein said step of applying said second levelat said control input comprises connecting latching circuitry havingfirst and second latching circuitry nodes to said first and referencenodes, whereby said latching circuitry establishes said complementarylogic levels on said first and second latching circuitry nodes.
 49. Amethod as claimed in claim 48, further comprising in response to saidsense amplifier enable signal, selectively applying a common potentialto said first and second latching circuitry nodes.
 50. A method asclaimed in claim 48, further comprising activating said referencecurrent source a predetermined interval after said application of saidsense amplifier enable signal.